Semiconductor devices are fabricated in wafer form and tested electrically before packaging begins. Some semiconductor devices, such as certain imagers, are very sensitive to ESD, having gate oxides as thin as 400 angstroms (.ANG.) with capacitances of the order of femtofarads (fF). The breakdown voltage of these gates can be as low as 50 to 75 volts, and will be proportionately lower for thinner gate dielectrics. The devices become particularly sensitive to small electrostatic charges during and after wafer dicing. These factors often result in significant yield losses in spite of precautionary measures utilized in manufacturing processes and areas.
An effective method of ESD protection is utilized beginning with wire bonding when all external package pins, which are electrically connected, are connected via the wires to the bond pads. This eliminates most of the danger of ESD related failures during the remainder of the packaging process by avoiding the possibility of voltage gradients within the semiconductor device. However, as each wire is being connected during wire bonding, voltage gradients external to the semiconductor or within the semiconductor structures can be transmitted via the wire to sensitive gates, causing damage. Of course, this method does not protect the devices prior to wire bonding; during dicing, second optical inspection, and die bonding.
Imager devices are also sensitive to dirt and debris. To protect our images during dicing, an intrinsically dirty operation, we use a polymeric layer, called a dicing protection layer (DPL) which is applied following the wafer electrical test. After dicing, the imager chip is bonded into a package, and the bonding epoxy is cured. Following curing, the DPL is removed, along with the dirt and debris, using a solvent cleaning system.